JFET Shootout

[Chuck D. Bones]

Here goes...

When the switch is in the up position, the gate is shorted to the source. That is the test condition for measuring Idss. The DMM is connected across the 100Ω resistor. We calculate the drain current from the voltage drop (V) across the 100Ω resistor.
Idss = V / 100Ω

When the switch is in the down position, the gate is connected to GND. The source is connected to GND thru the 1M-10M resistor. The DMM measures the voltage between gate (GND) and source. That's Vgs. The drain current, Id, flows thru the 1M-10M resistor, which causes the drain current to be very low, between a few hundred nA and a few μA, depending on the exact resistor value and Vp. That's the test condition for measuring Vp (Vgs,off). The DMM reads Vp directly. Note that Vp = -Vgs,off.

 

[owlexifry]

Is this the correct circuit?

i used that exact JFET matcher to select the JFETs for my phase 90 build (the smaller board).
it works as intended.
the layout is fine.

That's for someone else to figure out. I have lost interest in Tagboardeffects. Too many Vero layouts with errors.

interesting complaint...
i haven't actually found one yet with any errors.
- klon, about x10 other overdrives, cab sim, equinox II reverb, CE-2, phase 90, and just recently a mutron phasor ii.
zero issues with any layout.

 

[owlexifry]

Is there an explanation of how that circuit works? I can kinda make some educated guesses…

this is for that 'smaller' JFET tester

the larger one is discussed on this page:

http://geofex.com/Article_Folders/fetmatch/fetmatch.htm

 

[Chuck D. Bones]

The vast majority are OK, but I found a few over the years that either had errors on the Vero or were designed to a dubious schematic. I know Mark works hard at it, and I respect that.

 

[owlexifry]

The vast majority are OK, but I found a few over the years that either had errors on the Vero or were designed to a dubious schematic. I know Mark works hard at it, and I respect that.

fair call, i guess it can be a bit unsettling when layouts are posted without any schematics/references.

 

[giovanni]

Here goes...

When the switch is in the up position, the gate is shorted to the source. That is the test condition for measuring Idss. The DMM is connected across the 100Ω resistor. We calculate the drain current from the voltage drop (V) across the 100Ω resistor.
Idss = V / 100Ω

When the switch is in the down position, the gate is connected to GND. The source is connected to GND thru the 1M-10M resistor. The DMM measures the voltage between gate (GND) and source. That's Vgs. The drain current, Id, flows thru the 1M-10M resistor, which causes the drain current to be very low, between a few hundred nA and a few μA, depending on the exact resistor value and Vp. That's the test condition for measuring Vp (Vgs,off). The DMM reads Vp directly. Note that Vp = -Vgs,off.

I’m surprised none of these quantities depend on Vcc! How do you choose the 1M-10M resistor?

 

[Chuck D. Bones]

I’m surprised none of these quantities depend on Vcc!

Idss & Vp are only weakly dependent on Vds. FETs are pretty close to an ideal current source.

How do you choose the 1M-10M resistor?

The exact resistance is only important when we compare our Vp measurement to the datasheet limits. Let's use a couple of examples.

The 2N5952's Vgs,off spec is -1.3V to -3.5V measured with Vds = 15V and Id = 100nA. We should really use 18V power for maximum accuracy, but 9V will be good enough. For Id to be 100nA, the test resistor should be the expected Vp / Id. We expect Vp to land in the middle of the spec range, so the test resistor should be 2.4V / 100nA = 24M. Our DMM input impedance is 10M (might be only 1M if it's a cheapie). Even if we leave the test resistor out, the test resistance is our DMM, 10M. This will make our Vp reading a little on the low side, but it's good enough for what we're doing.

The situation is even worse with the J201 because the Vgs,off range is -0.3V to -1.5V and the Id is 10nA. The test resistor would have to be 0.9V / 10nA = 90M to match the datasheet test conditions.

The only exception I've run across so far is the J113. Vgs,off range is -0.5V to -3.0V with Id = 1μA. In this case, the test resistor should be 1.75V / 1μA = 1.75M.

This is why I usually leave out the 1M-10M resistor and use the 10M input impedance of my DMM as the test resistor.

 

[giovanni]

So that’s an open circuit and the DMM closes it?

 

[Chuck D. Bones]

Correct.

 

[The Gator]

So I broke down and bought a fancy schmancy tester that seems to test Jfets well, among other things.

https://www.circuitspecialists.com/products/CSI-TC2?gclid=CjwKCAiAuOieBhAIEiwAgjCvcmno_PMRCWRPmc9aWubuSjccWjXRe0ICRKwqEoFon23uLN22zwK59BoCfQQQAvD_BwE

So I tested a batch of TO92 j201s I purchased that were allegedly good for pedal projects and it seems like they are. Now I am soldering up smd J201s to adapter boards and testing them as well.
Some of these are testing really close to each other as far as Idss and Vgs.

My question is, what is considered close enough to matching? How much of a deviation?

Thanks
Gator

 

[Chuck D. Bones]

Depends on the pedal. In most instances, you want to match the JFETs to the circuit requirements, not to each other. In the case of phasers, you want a Vp that's compatible with the circuit and then match them to each other so the phase-shift stages track. I don't know of a specific pass/fail criteria. I would think that getting Vp and Idss within 10% should be adequate.

According to the description on the webpage, that tester does not measure Vp or Idss. It measures Id at some arbitrary Vgs. Vp and Idss will be larger than the numbers reported.

Let use know how well that tester does with Germanium.

 

[The Gator]

Well that sucks...lol. I guess I totally missed the boat. I have failed miserably and brought shame to my village...
I will test some germanium transistors after dinner and report back.

 

[Chuck D. Bones]

If the DSO works well then it's still worth the $.

 

[The Gator]

Ok here some data from a pair of 2N404 transistors

 

[Chuck D. Bones]

We're drifting off-topic here, but those are the highest gain 2N404s I've seen. The other numbers are believable. Can we see the transistor marking? There are some Ge trannys coming out of China marked 2N404 with a Motorola logo and a recent LDC.

 

[The Gator]

They were purchased from Amplified Parts I believe.

 

[Chuck D. Bones]

That's a Solid State Inc. logo. SSI is a distributor in Noo Joyzee. Apparently they have bought up some PNP Ge die, had them packaged & labeled. They show tens of thousands of them in stock. They provide price quotes on request. They also show 2N1308, 2N1309, AC127 and AC187 in stock.

 

[The Gator]

Back to Jfets,
Yeah I thought I had found a less expensive tester to quickly test, sort, and match jfets.
Is there something you recommend Chuck? Besides a DCA75?

 

[Chuck D. Bones]

I just use a DMM and the circuit in post #43, above. I don't have one built per se, I just assemble it in a corner of a breadboard whenever I need it. If all I want to do is check for aliveness or confirm the pinout, then I use a CCTT.

 

[giovanni]

That's a Solid State Inc. logo. SSI is a distributor in Noo Joyzee. Apparently they have bought up some PNP Ge die, had them packaged & labeled. They show tens of thousands of them in stock. They provide price quotes on request. They also show 2N1308, 2N1309, AC127 and AC187 in stock.

Where did you find all that?