#### Chuck D. Bones

##### Circuit Wizard

This time we'll focus on the Fuzz Face. The Fuzz Face has a long and colorful history that is beyond the scope of this discussion. The original FFs were built with PNP Germanium transistors because that's what the pedal builders had to work with. In this discussion, I'll talk about NPN transistors. It's simpler that way because all of the voltages are positive and we don't have to stand on our heads when we look at the schematics. All the same principles apply with PNP or NPN, Germanium or Silicon. I'll start off with Si because we don't have to concern ourselves with leakage. Later in the discussion, we'll take leakage into account.

Here's the classic Fuzz Face circuit:

So what exactly do we mean when we talk about biasing a Fuzz Face? Usually, we're measuring or setting the DC voltage on Q2's collector. But the DC bias affects both transistors, so in the broader sense, we mean the collector currents of both transistors and the emitter and collector voltages on Q2.

For the purposes of evaluating the DC bias, we will treat all three capacitors as open circuits since they block DC. There is a DC feedback loop from Q1's collector to Q2's base and then back to Q1's base thru R1. It's a negative feedback loop because there are an odd number of inversions as we go around the loop. In other words, if something makes Q2's collector current go up, then Q2's emitter voltage rises. A rise in Q2's emitter voltage increases the current thru R1 into Q1's base. This makes Q1's collector voltage drop, which is the same a Q2's base voltage. Lowering Q2's base voltage reduces Q2's collector current, restoring the bias point. With me so far? Good.

Most of the time, we pick a bias point where neither transistor is cut-off or saturated (more on that later). This is important because the feedback loop only works as long as both transistors are operating in a linear region. Now let's analyze the transistor voltages & current. Engineers are both clever & lazy; we try to simplify analysis tasks whenever possible. We'll start out by assuming that Q1 and Q2's base currents are very small, almost zero. If Q1 and Q2 have hFE of 100 or more, then the error caused by this assumption is small. Later on we'll go back and account for base current for the cases where the transistors have low hFE and/or leakage.

Four factors influence Q2's collector current: R1, the FUZZ pot's resistance (Rf), Q1's base current and Q1's Vbe. We've already said we're going to assume Q1's base current is zero, so the voltage drop in R1 is zero because V = i * R. So now we're down to two factors: Rf and Vbe. Vbe is around 0.65V for silicon transistors at room temp. Let's set Rf to 1K, because that's a typical value. The voltage at both ends of R1 is 0.65V, which means that the voltage at Q2's emitter is 0.65V. Q2's emitter current is 0.65V / 1K = 650μA. We're assuming a high hFE, so emitter current is more-or-less equal to collector current. Now we can calculate Q2's collector voltage. We'll assume R3 = 470Ω and R4 = 4.7K (typical values). Q2's collector current flows from the 9V battery thru R3 & R4. Q2's collector voltage is Vcc - (R3 + R4) * Ic = 9V - (5170Ω * 650μA) = 3.36V. If we want to make Q2's Vc higher, we can reduce R4. Many FF's have a trimmer for R4.

That was easy, let's add on another layer by accounting for base current. We'll let both transistors have hFE = 50 and we'll set R2 = 33K, a typical value. Again, we'll be clever/lazy and start off with the assumption (sounds better than "guess") that Q2's Ic = 650μA. If we want to be exact, we have to solve equations for both transistors at the same time, but because we're making small changes from our initial calculation, we can simplify things and calculate Q1's and Q2's operating points one at a time and see what happens. We'll start with Q2. We're assuming that Ic = 650μA and hFE = 50, so Ib = 650μA / 50 = 13μA. Q2's emitter is at 1 Vbe, so Q2's base is at 2 Vbe = 1.3V. Now we can calc the current in R2. IR2 = (Vcc - 2*Vbe) / R2 = 355μA. Of that 355μA, 13μA goes into Q2's base and the rest goes into Q1's collector. Now we can calculate Q1's operating point. Ic = 355μA - 13μA = 342μA. Q1 has hFE = 50, so Q1's base current is Ib = Ic / hFE = 342μA / 50 = 6.8μA. Almost done, we now have to account for the voltage drop in R1. We'll let R1 = 100K. The voltage drop is 6.8μA * 100K = 680mV. That's about the same as Vbe, so it's significant. It means that Q2's emitter voltage and collector current are over twice what we initially guessed. If we increase Q2's Ic, we'll have to reduce R4 to keep Q2 from saturating. Good thing we have a trimmer there!

We'll take one more pass. Q2's Ie = (650mV + 684mV) / Rf = 1.334mA. Ib = Ie / (hFE + 1) = 26μA. I used hFE + 1 in the calculation because Ie = Ib + Ic. So now Q1's Ic is a little small than the last pass because Q2 is taking more of R2's current to feed it's base. Q1's Ic = 355μA - 26μA = 329μA. That means Q1's Ib = 329μA / 50 = 6.6μA. The voltage drop in R1 is now 660mV instead of the 680mV we calculated on the last go-round. Close enough! We could have done this all in one pass if we were willing to slog thru some 2nd-year high-school algebra. I figured most of us were not willing.

So what do we do with all of this information? We can look at it qualitatively and see that hFE definitely makes a difference in the bias point. We can also see that if we're willing to tweak one or two resistors, we can use pretty much any hFE we like.

I mentioned leakage at the beginning of this discussion, so let's look at that. Leakage in a Ge transistor behaves like there is an extra resistor connected between base & collector. That resistor injects additional current into the base which affects the bias. Leakage in Q2 doesn't have much effect because Q1 will drain away the excess current thru it's collector. It affects the overall bias point, but not much. Leakage in Q1 is a whole different story because the only place for excess base current to go is backwards thru R1. The feedback loop will lower Q2's emitter voltage in an effort to reduce Q1's base current. Let's look at some numbers. Suppose that Q1 has hFE = 50, like before, but now Iceo (collector leakage current) = 300μA. Iceo is the collector current with no external base current. All of the base current is from collector-base leakage. That means the internal base leakage current is Iceo / hFE = 6μA. That's 6μA that doesn't have to come from R1, so R1's current just went down from 6.6μA to 0.6μA. Holy Shit Batman, that an 11x reduction! As a result, the voltage across R1 goes to down to 60mV (from 660mV) and Q2's emitter voltage goes down to 710mV (from 1.334V). You can see the ripple effect. The leakage in Q1 has caused Q2's collector current to be about half what it was when Q1 had no leakage. This example illustrates that 300μA leakage in Q1 is close to the upper bound of what would be acceptable in this circuit. Another take-away is that since leakage is very temperature sensitive, using a leaky Ge transistor for Q1 can cause a Fuzz Face to malfunction when exposed to the high temperatures from stage lighting. Hybrid FF circuits like we see in the Skreddy Screw Driver use a high-gain Si tranny for Q1 and a Ge tranny for Q2. We get the Germanium tone and the stability of Silicon.

One last thing: Gating. Through this entire discussion we've kept Q1 and Q2 in the linear region. What happens if we deliberately (or otherwise) skew the bias point so that Q2 saturates? Two things happen: the feedback loop is broken and Q2's gain approaches zero. The precipitous drop in Q2's gain kills the guitar signal and we have gating. If we put enough guitar signal in, that signal will drive Q2 out of saturation and back into the linear region. As the guitar signal decays, Q2 slips back into saturation and the output signal cuts off. That ripping velcro tone is saturation setting in. Gating can be achieved simply by raising R3 or R4 until Q2 saturates. We could also fiddle with R1, which is how the Woolly Mammoth does it, or vary R3 and Rf, which is how the Fuzz Factory does it. It all comes down to pushing the bias point to the extreme.

Here's the classic Fuzz Face circuit:

So what exactly do we mean when we talk about biasing a Fuzz Face? Usually, we're measuring or setting the DC voltage on Q2's collector. But the DC bias affects both transistors, so in the broader sense, we mean the collector currents of both transistors and the emitter and collector voltages on Q2.

For the purposes of evaluating the DC bias, we will treat all three capacitors as open circuits since they block DC. There is a DC feedback loop from Q1's collector to Q2's base and then back to Q1's base thru R1. It's a negative feedback loop because there are an odd number of inversions as we go around the loop. In other words, if something makes Q2's collector current go up, then Q2's emitter voltage rises. A rise in Q2's emitter voltage increases the current thru R1 into Q1's base. This makes Q1's collector voltage drop, which is the same a Q2's base voltage. Lowering Q2's base voltage reduces Q2's collector current, restoring the bias point. With me so far? Good.

Most of the time, we pick a bias point where neither transistor is cut-off or saturated (more on that later). This is important because the feedback loop only works as long as both transistors are operating in a linear region. Now let's analyze the transistor voltages & current. Engineers are both clever & lazy; we try to simplify analysis tasks whenever possible. We'll start out by assuming that Q1 and Q2's base currents are very small, almost zero. If Q1 and Q2 have hFE of 100 or more, then the error caused by this assumption is small. Later on we'll go back and account for base current for the cases where the transistors have low hFE and/or leakage.

Four factors influence Q2's collector current: R1, the FUZZ pot's resistance (Rf), Q1's base current and Q1's Vbe. We've already said we're going to assume Q1's base current is zero, so the voltage drop in R1 is zero because V = i * R. So now we're down to two factors: Rf and Vbe. Vbe is around 0.65V for silicon transistors at room temp. Let's set Rf to 1K, because that's a typical value. The voltage at both ends of R1 is 0.65V, which means that the voltage at Q2's emitter is 0.65V. Q2's emitter current is 0.65V / 1K = 650μA. We're assuming a high hFE, so emitter current is more-or-less equal to collector current. Now we can calculate Q2's collector voltage. We'll assume R3 = 470Ω and R4 = 4.7K (typical values). Q2's collector current flows from the 9V battery thru R3 & R4. Q2's collector voltage is Vcc - (R3 + R4) * Ic = 9V - (5170Ω * 650μA) = 3.36V. If we want to make Q2's Vc higher, we can reduce R4. Many FF's have a trimmer for R4.

That was easy, let's add on another layer by accounting for base current. We'll let both transistors have hFE = 50 and we'll set R2 = 33K, a typical value. Again, we'll be clever/lazy and start off with the assumption (sounds better than "guess") that Q2's Ic = 650μA. If we want to be exact, we have to solve equations for both transistors at the same time, but because we're making small changes from our initial calculation, we can simplify things and calculate Q1's and Q2's operating points one at a time and see what happens. We'll start with Q2. We're assuming that Ic = 650μA and hFE = 50, so Ib = 650μA / 50 = 13μA. Q2's emitter is at 1 Vbe, so Q2's base is at 2 Vbe = 1.3V. Now we can calc the current in R2. IR2 = (Vcc - 2*Vbe) / R2 = 355μA. Of that 355μA, 13μA goes into Q2's base and the rest goes into Q1's collector. Now we can calculate Q1's operating point. Ic = 355μA - 13μA = 342μA. Q1 has hFE = 50, so Q1's base current is Ib = Ic / hFE = 342μA / 50 = 6.8μA. Almost done, we now have to account for the voltage drop in R1. We'll let R1 = 100K. The voltage drop is 6.8μA * 100K = 680mV. That's about the same as Vbe, so it's significant. It means that Q2's emitter voltage and collector current are over twice what we initially guessed. If we increase Q2's Ic, we'll have to reduce R4 to keep Q2 from saturating. Good thing we have a trimmer there!

We'll take one more pass. Q2's Ie = (650mV + 684mV) / Rf = 1.334mA. Ib = Ie / (hFE + 1) = 26μA. I used hFE + 1 in the calculation because Ie = Ib + Ic. So now Q1's Ic is a little small than the last pass because Q2 is taking more of R2's current to feed it's base. Q1's Ic = 355μA - 26μA = 329μA. That means Q1's Ib = 329μA / 50 = 6.6μA. The voltage drop in R1 is now 660mV instead of the 680mV we calculated on the last go-round. Close enough! We could have done this all in one pass if we were willing to slog thru some 2nd-year high-school algebra. I figured most of us were not willing.

So what do we do with all of this information? We can look at it qualitatively and see that hFE definitely makes a difference in the bias point. We can also see that if we're willing to tweak one or two resistors, we can use pretty much any hFE we like.

I mentioned leakage at the beginning of this discussion, so let's look at that. Leakage in a Ge transistor behaves like there is an extra resistor connected between base & collector. That resistor injects additional current into the base which affects the bias. Leakage in Q2 doesn't have much effect because Q1 will drain away the excess current thru it's collector. It affects the overall bias point, but not much. Leakage in Q1 is a whole different story because the only place for excess base current to go is backwards thru R1. The feedback loop will lower Q2's emitter voltage in an effort to reduce Q1's base current. Let's look at some numbers. Suppose that Q1 has hFE = 50, like before, but now Iceo (collector leakage current) = 300μA. Iceo is the collector current with no external base current. All of the base current is from collector-base leakage. That means the internal base leakage current is Iceo / hFE = 6μA. That's 6μA that doesn't have to come from R1, so R1's current just went down from 6.6μA to 0.6μA. Holy Shit Batman, that an 11x reduction! As a result, the voltage across R1 goes to down to 60mV (from 660mV) and Q2's emitter voltage goes down to 710mV (from 1.334V). You can see the ripple effect. The leakage in Q1 has caused Q2's collector current to be about half what it was when Q1 had no leakage. This example illustrates that 300μA leakage in Q1 is close to the upper bound of what would be acceptable in this circuit. Another take-away is that since leakage is very temperature sensitive, using a leaky Ge transistor for Q1 can cause a Fuzz Face to malfunction when exposed to the high temperatures from stage lighting. Hybrid FF circuits like we see in the Skreddy Screw Driver use a high-gain Si tranny for Q1 and a Ge tranny for Q2. We get the Germanium tone and the stability of Silicon.

One last thing: Gating. Through this entire discussion we've kept Q1 and Q2 in the linear region. What happens if we deliberately (or otherwise) skew the bias point so that Q2 saturates? Two things happen: the feedback loop is broken and Q2's gain approaches zero. The precipitous drop in Q2's gain kills the guitar signal and we have gating. If we put enough guitar signal in, that signal will drive Q2 out of saturation and back into the linear region. As the guitar signal decays, Q2 slips back into saturation and the output signal cuts off. That ripping velcro tone is saturation setting in. Gating can be achieved simply by raising R3 or R4 until Q2 saturates. We could also fiddle with R1, which is how the Woolly Mammoth does it, or vary R3 and Rf, which is how the Fuzz Factory does it. It all comes down to pushing the bias point to the extreme.

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