Cybercow
Well-known member
I'm looking for assistance in analyzing this circuit. What I can make of it is that it seems to pass signal when certain conditions of the lower section turns the JFET (Q102 2N5457) off. I'm guessing the lower section captures the signal's attack transient and turns the JFET on or off. A single-shot delay of some sort?
The power supply is dual-rail ±12V DC arrangement.
Anyone willing to run it thru LTSpice? (I personally don't know LTSPice.)
The power supply is dual-rail ±12V DC arrangement.
Anyone willing to run it thru LTSpice? (I personally don't know LTSPice.)
