Antithesis not splitting V+

Hi all,
Creating a Si version of the Antithesis Fuzz and it isn't passing a signal through the 2 transistors. My troubleshooting seems to indicate that there is a problem with the Vcc. At all points from the schematic that should be seeing Vcc are coming up as 9.2V. So my guess is something is shorting it to V+ but I'll be damned if I see anything wrong. I reflowed everything and confirmed all components are correct and oriented properly.
Would love an extra set of eyes here or some ideas of why the voltage isn't being split as intended. FWIW I built the Ge version at the same time as this and it works perfectly.

Thanks all.
 

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