This Week on the Breadboard: the Subdecay Variac - highly modified

[Chuck D. Bones]

Most of 'em meet the Vp and Idss spec for 2N5457. I have not measured gfs yet.

 

[temol]

Did you try to lower gain of the first stage? Looks like first stage is already clipping the signal quite a lot. I'm on vacation now so I'm not able to breadboard the circuit now. I'm just looking @ ltspice simulation.

 

[fig]

I'm on vacation now so I'm not able to breadboard the circuit now.

We all feel just terrible about that too.

 

[Chuck D. Bones]

When I play thru it, there is some mild distortion even with PREAMP & POWER AMP at zero. It's supposed to be a distortion pedal, so I don't mind if there is no 100% clean setting. I have not tried lowering the gain on the breadboard yet. In simulation, taking R4 down to 27K and R13 down to 4.7K drops the gain ~6dB and keeps the drain voltage about the same. That's probably enough to get into clean territory.

Bummer that you forgot to take your breadboard on vacation. I had that happen once and I feel your pain.

 

[temol]

Bummer that you forgot to take your breadboard on vacation. I had that happen once and I feel your pain.

Never again...

But.... while drinking afternoon coffee I played a little bit with ltspice.
This is my modified first stage. In order to keep frequency response more or less intact I removed R13 and C9, increased C1 and C2, lowered C3.

 

[fig]

Goodie, I just got mine working. A half-dozen rookie mistakes, so I'm thrilled! (up until now, rookie-level was way beyond my capacitance...er capacity).

 

[Chuck D. Bones]

Never again...

But.... while drinking afternoon coffee I played a little bit with ltspice.
This is my modified first stage. In order to keep frequency response more or less intact I removed R13 and C9, increased C1 and C2, lowered C3.
View attachment 14352 View attachment 14353View attachment 14354

Looks like the drain voltage is too low in your sim. What's the input amplitude?

I finally found the J2N5457 model in the LTSpice library.

 

[Chuck D. Bones]

Stock values run the JFETs too cold in the sim.



Reducing R3 & R7 centers the stage1 & stage2 voltages for maximum headroom. Input amplitude at time = 0 is 500mVp-p which is pretty strong for most pickups. At that drive level, there is still some distortion in the 1st stage, but it's much less than before I altered the bias.

 

[temol]

Input signal here was 400mV (800mV p-p). It's possible that we have different 2N5457 models.
Here's mine:
.MODEL 2N5457 NJF(VTO=-1.8 BETA=0.00135 LAMBDA=0.001 RD=35 RS=31.5 CGS=2.25E-12 CGD=6E-12 KF=6.5E-17 AF=0.5 )
Vp -1.8V, Idss around 3.8mA

 

[Chuck D. Bones]

The one I pulled from the library is this:

.MODEL J2N5457 NJF(Beta=1.125m Betatce=-500m Rd=1 Rs=1 Lambda=2.3m Vto=-1.372 Vtotc=-2.5m Is=181.3f Isr=1.747p N=1 Nr=2 Xti=3 Alpha=2.543u Vk=152.2 Cgd=4p M=311.4m Pb=500m Fc=500m Cgs=4.627p Kf=1.045e-002f Af=1)

In a (simulated) test circuit,
Idss = 2.16mA
Vgs(off) = -1.36V

 

[fig]

I'll still have to bias when the other FETs arrive, but it's working. I ditched the volume pot. I was too liberal with spacing at the start and you don't regain it. I could re-route I guess, but prolly not. OUT is straight from the R25/C19 node.

(I added the tropical fishy just for you Chuck)

 

[Chuck D. Bones]

Sweet!

"You're gonna need a bigger boat breadboard!"

I'm about to plug some 2N5457s into mine.

 

[fig]

..and? It's been 2 days. I didn't count that many FETs.
I'm swinging back to this after a brief detour with self-biasing. I'm feeling muuch better now.

 

[Chuck D. Bones]

Oh, sorry, I got sidetracked and 4got to report my findings here. I recently purchased some 2N5457s that all tested at the cold end of the spec range (low Idss and Vgs,off). Tried them in the Variac and that circuit needed significant resistor tweaking to get them to bias correctly. I went back to the 2SK193s. Subdecay used 2N5457s in the Variac, but they must have been selected for higher Vgs,off. Plenty of JFETs will work in the Variac, it's just a matter for finding the right ones. That's life when building stuff with JFETs.

 

[temol]

I have not tested the circuit with your 5457 models yet (breadboard, ltspice) but first thing that caught my eye is different frequency of the input signal we use. 250Hz vs 660Hz. Probably different enough (considering frequency response of the circuit) to give slightly different apperance of the output signal.

 

[fig]

I biased the 2N5457s.

Q1D 4.428 @ 110KΩ
Q1D 4.396 @ 68KΩ

For those just starting (like me) using something like a trimmer on BreadBoard leads and then matching the correct resistor seems to be the way to go. I didn't have a 110KΩ, so I used 2-220KΩ in parallel.

Here's the output; I'm running a 500Hz sine at .50V

 

[Chuck D. Bones]

Whare are the source resistor values?

 

[fig]

man I must have something wrong...it's gated deep...whoops..incoming...where are the....hang on, let me get it back on the bench..

 

[fig]

Q1S 1.390vdc
Q2S 1.112vdc

Wait, are those what need biasing? Figures I'd do the wrong ones.

 

[Chuck D. Bones]

I asked about the size of source resistors, not the source voltage.