May benefit from an output stage after these, even just a jfet buffer to keep output impedance stable. Also, after clipping and filtering, the output level could be quite low.
Also. Not sure about the VCC link to U2.1 through R6. Wouldn't R6 decrease VCC and through the AC signal below VCC? Maybe this is fine. I just woke up so...
It looks OK to me, it's just drawn a little different.
It might look more familiar drawn like this:
I don't see anything that immediately stands out as a problem. Normally you'd have an input coupling capacitor between the input and the gate of U1, but not always, considering it's a JFET input stage. Like @jwin615 pointed out, you're missing the VREF voltage divider but I'm assuming you just haven't gotten there yet.