Proposition JFET J201 biasing

[shawnee]

Hello everyone,
I just finished building the Proposition Distortion and it functions (passes affected signal and all controls work but it doesn't seem to have the gain I thought it would. I'm thinking its a JFET bias issue (using an old Fairchild J201). I'm getting: Source= 8.6v, Drain=8.6v, and Gate=6.1v (Vgs= 0.1v or would that be -0.1v?) using the 6.2M and 5.1M resistors.

IC100
1- 9.1
2- 4.6
3- 0.0
4- 0.1
5- 0.3
6- 4.2
7- 5.6
8- 9.1

All TL072's
1- 8.6
2- 8.6
3- (8.1-8.6)
4- 0
5- (8.2-8.6) except IC3 (0.4)
6- 8.6
7- 8.6
8- 17
Any thoughts?

 

[Cybercow]

The JFET will not interfere with the Gain aspect. The JFET is there for the compression when the Gain is turned down. As the Gain is turned up, the compression aspect is diminished. [ Using the default bias resistor values, the selected JFET should exhibit (measure) a Vgs(Off) of about -1.00V, ±0.07V ]

In my experience, the Gain control just adds to the distortion and doesn't really increase the volume much.

 

[shawnee]

Thank you so much for the reply. I'm getting about -1.0v on a different J201 but still getting about 6.1v on the gate. Does it matter what the other voltages are? (I may be getting mixed up with standard transistors thinking I need to have 4.5v.

 

[Cybercow]

Thank you so much for the reply. I'm getting about -1.0v on a different J201 but still getting about 6.1v on the gate. Does it matter what the other voltages are? (I may be getting mixed up with standard transistors thinking I need to have 4.5v.

The voltage at the gate doesn't matter so much in this circuit. The JFET so used in this application acts more like a fast-reacting variable resistor, "clamping" the signal in unison with the pile of diodes/LEDs to actuate or not. This creates a simple compression effect that only works when the Gain pot is turned down.

Also, a JFET is a "symmetrical" device; meaning the Drain and Source legs can be swapped without issue. So the voltages at the Gate, Drain & Source are not going to make any sense with regard to standard transistor biasing.

With the Gain control turned fully counter-clockwise, you should be able to hear some compression on the attack transient of the guitar's plectrum. As the Gain control is turned up, that compression affect of the JFET will diminish as the opamp is push further into a higher gain. But you should still be able able to experience a significant gain, (compared to when the pedal is bypassed), in overall volume with the Gain turned down and the Volume turned up.

I don't understand what you mean when you say "I'm getting about -1.0v on a different J201 but still getting about 6.1v on the gate."
How & where are you measuring -1.0V?

 

[shawnee]

The -1.0v is from gate to source. The 6.4v is from gate to Gnd. I could swear I was getting -1.0v but now I seem to get 0.15v gate to source. The Vgs is really all over the place almost like it is being affected by a capacitor. Kinda up and down between .15 and 1.0.

 

[Cybercow]

How are you measuring the Vgs(Off) parameter?
The best way I know how to do it is with a Peak Atlas DCA75.

 

[shawnee]

I don't have a Peak. I'm just measuring gate to source with the J201 in circuit. How do you bias the JFET if it's not in circuit?

 

[Cybercow]

I don't have a Peak. I'm just measuring gate to source with the J201 in circuit. How do you bias the JFET if it's not in circuit?

The JFET in this circuit cannot be properly set up if it is not in circuit. However, it can be properly selected by measuring the Vgs(off) with a Peak Atlas DCA75 (or similar tool) or by setting up a test jig like found in the attached image. When a JFET exhibits a Vgs(off) of -1.00V ±0.05V, it is perfect to use in this circuit with the default values of RB101 & RB102. Otherwise, the values of RB101 & RB102 need to altered to agree with the measured Vgs(off).



The JFET is not "biased" here. Rather the "compression bias" resistors are set to near the Vgs(off) so the cut off voltage of the JFET turns it on in order to open the signal path to ground at the initial attack transient of the guitar signal at that opamp; creating a simple compression circuit.

The best method to ensure the JFET is actuating its compression task in this circuit is to arrange the following test setup. With the circuit being fed a 1KHz 1.00V (pp) audio signal, the values of the two compression biasing resistors need to set at values where signal voltage reads ~2.65v ±0.25v at the output (pin #7) of IC1.2

 

[shawnee]

Thank you so much. I will have to build one and see what I get.