Fun with CMOS - part 1 - The CMOS Raincoat

[Chuck D. Bones]

Good question. It's not straightforward to calculate. LTSpice is fairly accurate with transistor stages like the Raincoat, but the CMOS gain stages are difficult to calculate or simulate accurately because the behavior in the linear mode is not specified in the datasheet or controlled in manufacturing. I have LTSpice models of generic CMOS inverters, but because the actual devices vary so much, the simulations are not particularly accurate.

The previous stage has a non-zero output impedance, so that is in effect the input resistor of the next stage. By the same token, the input impedance of a CMOS inverter with feedback is low, so without an input resistor it loads the output of the previous stage. These impedances are non-linear and frequency-dependent, which further complicates matters. CMOS gain stages running in linear mode are capable of a max gain around 10x to 20x, so that influences the overall gain and freq response as well. The behavior is also influenced by the rail voltage. I've found that there is a sweet spot between 4V and 5V where the gain is highest. What I'm getting at is this: our best move is to breadboard and test the circuit.

 

[cdwillis]

I have a couple 4049ube chips I bought to play around with that I need to throw on a breadboard. Might finally tackle it tomorrow because I'm still fiddling with some distortion circuit on the "spare" breadboard.

 

[Chuck D. Bones]

My recommendations:
Keep it simple. Start with just two inverters. Adjust the rail voltage.
CD4049s manufactured by Texas Instruments are noisy. They're fine when used as digital parts, but not so good as analog parts. For reasons unknown to me, the CD4007s manufactured by Texas Instruments are quiet. That's why I prefer to design circuits with CD4007 over CD4049. I have some vintage CD4049s from Hitachi, National, Signetics and RCA that are quiet, but they are hard to find.