temol
Well-known member
How dare you...
Fun with CMOS - part 3 - Emma ReezaFratZitz (with Boneyard mod)
- Thread starter Chuck D. Bones
- Start date
How dare you...
MichaelW
Well-known member
I just ordered these based on YOUR recommendation.......
Chuck D. Bones
Circuit Wizard
NIIIIIIIIIIIIIIIIIIIIIIIIIIIIIICE!
How do CMOS gates differ from op-amps when it comes to configuring their gain and frequency response? I normally use https://nz.element14.com/op-amp-gain-calculator but don't know the theory when it comes to CMOS.
Chuck D. Bones
Circuit Wizard
They differ in just about every way possible. The simple gain calculation is not accurate and the accurate gain calculation is not simple.
Opamps have an open-loop gain of 100,000 or more. In linear mode, CMOS gates have an open-loop gain somewhere between 10 and 100. It varies with power supply voltage and from part-to-part. This sets an upper limit on gain and it complicates the gain calculation because we have to account for the low open-loop gain.
CMOS gates can only be configured as inverting amplifiers be cause they do not have a + input.
Opamps have a very low output impedance, under 100Ω. In linear mode, CMOS gates have an output impedance of several KΩ or more. Because if that, loading reduces the open-loop gain. The feedback loop will load the gate unless we use very large resistor values. Large resistor values will interact with stray capacitance, limiting bandwidth. The next functional block in the circuit can also load the gate.
The two best options are LTSpice and breadboard testing. I do both. Even with all that, I expect a certain amount of variability from part-to-part.
Opamps have an open-loop gain of 100,000 or more. In linear mode, CMOS gates have an open-loop gain somewhere between 10 and 100. It varies with power supply voltage and from part-to-part. This sets an upper limit on gain and it complicates the gain calculation because we have to account for the low open-loop gain.
CMOS gates can only be configured as inverting amplifiers be cause they do not have a + input.
Opamps have a very low output impedance, under 100Ω. In linear mode, CMOS gates have an output impedance of several KΩ or more. Because if that, loading reduces the open-loop gain. The feedback loop will load the gate unless we use very large resistor values. Large resistor values will interact with stray capacitance, limiting bandwidth. The next functional block in the circuit can also load the gate.
The two best options are LTSpice and breadboard testing. I do both. Even with all that, I expect a certain amount of variability from part-to-part.