Help with split rail FET circuit

R

rossbalch

Well-known member
Hey folks, I've been designing this Blackface-ish inspired preamp circuit. The thing is it inverts the output which I want to avoid. For stubborn reason I've been trying to avoid using another op amp for the task of re-inverting the signal, adding a bit of gain, and buffering the output. I've been using this circuit which works well enough but one half of the waveform buts up against the 12v rail. Given that I have -12v available as well I'm sure there must be a way to leverage that to make biasing easier. Honestly maybe the solution is just to use an op-amp, but either way I would like to learn about using discrete circuits with split rail.

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Well have you tried just putting the source and emitter resistors and J-FET's biasing 1M to -12V?

But more to the point, have you checked what kind of voltages you're currently getting on the J-FET and transistor?
 
Scruffie said:
Well have you tried just putting the source and emitter resistors and J-FET's biasing 1M to -12V?

But more to the point, have you checked what kind of voltages you're currently getting on the J-FET and transistor?
Click to expand...

Hmm, now the whole thing just acts as a buffer. Without -12v on the emitter of Q1 there is zero voltage on the output. At least before I was getting a gain of ~3 which is what I had wanted in the first place.

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Blackboarcult said:
On the top circuit: you are missing a resistor to ground at the positive input of the first opamp. Won't work well as is.

Bottom circuit: as Scruffie said :D
Click to expand...

Thanks, I think I will just scrap the first JFET buffer, it doesn't seem necessary really.
 
What are your bias voltages, the transistor buffer is relying on the J-FET in this situation for optimal bias.

Poor bias, poor signal swing and unfortunately, the J-FET's biasing is also impacting its gain.
 
rossbalch said:
Even though the input voltage is a perfect 1v ac sine wave in the simulation?
Click to expand...
Yes. Your sine wave is an ideal voltage source referenced to ground. It has zero output impedance and it's connected to the same node as your bias resistor which is not zero. So that node is forced to sit at ground no matter what. Either reference your sine wave to -12V as well or add a coupling capacitor between it and R1 so it doesn't upset your DC bias.
 
lowpitch said:
Yes. Your sine wave is an ideal voltage source referenced to ground. It has zero output impedance and it's connected to the same node as your bias resistor which is not zero. So that node is forced to sit at ground no matter what. Either reference your sine wave to -12V as well or add a coupling capacitor between it and R1 so it doesn't upset your DC bias.
Click to expand...

Ok so let's say instead the FET/BJT combo circuit is connected to the output of my "Recovery Tube" from the initial circuit, after R16, would I still need a coupling cap? Assuming you remove R11 to replace it with R1 from the FET/BJT circuit.
 
rossbalch said:
Ok so let's say instead the FET/BJT combo circuit is connected to the output of my "Recovery Tube" from the initial circuit, after R16, would I still need a coupling cap? Assuming you remove R11 to replace it with R1 from the FET/BJT circuit.
Click to expand...
Yes. The op amp is biased to ground via R9. Op amp output impedance is negligible, so that's where the output is going to sit at as well unless you add a coupling cap before the bias resistor connected to -12V.
 
lowpitch said:
Yes. The op amp is biased to ground via R9. Op amp output impedance is negligible, so that's where the output is going to sit at as well unless you add a coupling cap before the bias resistor connected to -12V.
Click to expand...

Awesome thanks for your help, I think I'm beginning to understand a bit more about DC and biasing here.
 
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