JFET Biasing - part 1

I spend a fair amount of time trying to make this as concise and readable as I could.

Intro
In theory, setting the bias on JFETs should be easy. In practice, not so much. Here are the details on why that is and what we can do about it.

Let's review some theory and get the math out of the way.

In may ways JFETs are ideal devices. At audio frequencies, the input and output impedances are so high we can treat them as infinite. Once set, the drain
current and gain are very stable. The gate current is essentially zero. That means any current that flows into the drain lead has only one way out: the source
lead. In other words, drain current equals source current.

The transfer function (drain current vs. gate voltage) of a JFET is:
1609709057352.png

If we do a little calculus, we can solve for the transconductance (gain):
1609709124179.png
Vgs is the voltage from gate to source, Gm is the transconductance, or how much the drain current changes when we change Vgs.

The good news is that if we know Vp and Idss, we know everything we need to know about what a JFET will do in a given circuit.

The bad news is that Vp and Idss vary a LOT from one device to another. Reading the datasheet is a good start, but in most cases we will have to measure each
device and either select them or tweak some resistor values. This is why JFET pedals contain trimpots.

Setting the Bias
What are we trying to accomplish when we set the bias of a transistor gain stage? Two things:
1. We want to set the headroom and clipping level.
2. We want to set the gain.

Here is a common JFET amplifier configuration found in pedals. Cs is optional. It increases the gain when Rs is large. If Cs is present, it may have a resistor or pot in series to set the gain. The drain current is set by Rs, Vp and Idss. The only restrictions are Id has to be smaller than Idss and the magnitude of Vp has to be smaller than the power supply voltage.
1609777057733.png
Since Vgs = -Id x Rs, we can replace Vgs in the equation with -Id x Rs and obtain the relationship between Vp, Idss, Id and Rs. Remember, Vp is always negative with N-channel JFETs.

1609709743704.png
Let's do a practical example. We'll use an MPF4393. A typical Vp for the MPF4393 is -1.75V. A typical Idss is 17.5mA. We'll use a 22K drain resistor and we want the drain voltage to be 6V. Power supply is 9V. The drain current we want is (9V-6V)/22K = 136uA. Now we run the formula above. The result is Rs = 11.7K. If the transistor we pull out of the bin has Vp and Idss right in the middle of the spec range, the drain voltage and drain current will be as expected. But what if Vp and Idss are both at the bottom end of the spec?

The equation for Id as a function of Rs is pretty damned messy so I'll spare you the gory details. When Rs = 15K, Vp = -0.5V and Idss = 5mA then Id = 31uA. That's less than 1/4 of the desired Id. To get Id = 136uA, we have to change Rs to 3K or pick another JFET. Depending on Cs and its series resistor, changing Rs will most likely alter the gain, which may or may not be ok. The other alternative is to cherry-pick the JFET. I buy JFETs in quantity so I can cherry-pick them. So far, I've been lucky that the JFETs I get are pretty close to the middle of their spec range. since there are no guarantees, it's good to have plenty of spares from which to choose.

One more example. We see this one in the Rat and some amp-in-a-box pedals. It's a source follower. The gain of this circuit is unity (0dB). Its sole purpose is to
have a high input impedance so it doesn't load the guitar, pedal or circuit that precedes it and have a low output impedance so it can drive the circuit, pedal or cable
that follows it.

There are three ways to bias a source-follower:
1. We can make the DC gate voltage zero volts and use Vp and Rs to set the bias.
2. We can make the gate voltage Vref and use Vref, Vp and Rs to set the bias.
3. We can DC couple the gate to the previous stage and use that stage's output voltage, Vp and Rs to set the bias.

Here's the Rat output buffer.
1609709978378.png
R8 and C9 ensure that the DC voltage on Q1's gate is 0V. Typical Vp for 2N5458 is -4V. That means Q1's source is at 4V and the drain
current is...

(let's not always see the same hands, class)

Id = Rs / Vp = 4V / 10K = 400uA.

For the 2N5458, Vp can be between -1V and -7V, so Vs and Id can be all over the place. If Vs is at 1V or 7V, then we've lost a fair amount of headroom and we could end up with Q1 saturating. The only solution with this circuit is to cherry-pick Q1 so we get a Vp that is somewhere between 1/3 and 2/3 of the power supply voltage.

Here's the Covert output buffer.

1609710181858.png
It makes its own Vref with R18 & R19. Those two resistors bias Q5's gate to 1/2 Vcc (4.5V). Typical Vp is -1.75V. That puts the bias point at:

Vs = 4.5V + 1.75V = 6.25V.

Id = 6.25V / 4.7K = 1.33mA.

For the MPF4393, Vp ranges from -0.5V to -3.0V. That means Vs can be as low as 5V or as high as 7.5V. 5V is not bad, it's near the midway point between Vcc and ground. But 7.5V has only 1.5V of headroom and Q5 will saturate during the loud parts of the notes. Here, we have some freedom. We can adjust R18 or R19 to obtain the desired Vs or pick another JFET out of the pile.

Last example. This is the 3rd stage in the M800 OD.

1609710280008.png
Q3 makes the gain in the 3rd stage. Q4 is a buffer that keeps the tone stack from loading Q3. Q4's gate voltage is the same as Q3's drain voltage (because they're connected). Lucky us! We can use TRIM3 to dial-in Q4's bias point. Vp for the J201 is -0.3V to -1.5V. We can set TRIM3 to give us something around 5V at Q4's source, which puts Q3's drain around 4V. Then we tweak by ear from there.

I'll save mu-amps for part 2.
 

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