JFET Biasing - part 1

I spent a fair amount of time trying to make this as concise and readable as I could.

Intro
In theory, setting the bias on JFETs should be easy. In practice, not so much. Here are the details on why that is and what we can do about it.

Let's review some theory and get the math out of the way.

In may ways JFETs are ideal devices. At audio frequencies, the input and output impedances are so high we can treat them as infinite. Once set, the drain
current and gain are very stable. The gate current is essentially zero. That means any current that flows into the drain lead has only one way out: the source
lead. In other words, drain current equals source current.

The transfer function (drain current vs. gate voltage) of a JFET is:


If we do a little calculus, we can solve for the transconductance (gain):



Vgs is the voltage from gate to source, Gm is the transconductance, or how much the drain current changes when we change Vgs.

The good news is that if we know Vp and Idss, we know everything we need to know about what a JFET will do in a given circuit.

The bad news is that Vp and Idss vary a LOT from one device to another. Reading the datasheet is a good start, but in most cases we will have to measure each
device and either select them or tweak some resistor values. This is why some JFET pedals contain trimpots.

Setting the Bias
What are we trying to accomplish when we set the bias of a transistor gain stage? Two things:
1. We want to set the headroom and clipping level.
2. We want to set the gain.

Here is a common JFET amplifier configuration found in pedals. Cs is optional. It increases the gain when Rs is large. If Cs is present, it may have a resistor or pot in series to set the gain. The drain current is set by Rs, Vp and Idss. The only restrictions are Id has to be smaller than Idss and the magnitude of Vp has to be smaller than the power supply voltage.

Since Vgs = -Id x Rs, we can replace Vgs in the equation with -Id x Rs and obtain the relationship between Vp, Idss, Id and Rs. Remember, Vp is always negative with N-channel JFETs.


Let's do a practical example. We'll use an MPF4393. A typical Vp for the MPF4393 is -1.75V. A typical Idss is 17.5mA. We'll use a 22K drain resistor and we want the drain voltage to be 6V. Power supply is 9V. The drain current we want is (9V-6V)/22K = 136uA. Now we run the formula above. The result is Rs = 11.7K. If the transistor we pull out of the bin has Vp and Idss right in the middle of the spec range, the drain voltage and drain current will be as expected. But what if Vp and Idss are both at the bottom end of the spec?

The equation for Id as a function of Rs is pretty damned messy so I'll spare you the gory details. When Rs = 15K, Vp = -0.5V and Idss = 5mA then Id = 31uA. That's less than 1/4 of the desired Id. To get Id = 136uA, we have to change Rs to 3K or pick another JFET. Depending on Cs and its series resistor, changing Rs will most likely alter the gain, which may or may not be ok. The other alternative is to cherry-pick the JFET. I buy JFETs in quantity so I can cherry-pick them. So far, I've been lucky that the JFETs I get are pretty close to the middle of their spec range. since there are no guarantees, it's good to have plenty of spares from which to choose.

One more example. We see this one in the Rat and some amp-in-a-box pedals. It's a source follower. The gain of this circuit is unity (0dB). Its sole purpose is to
have a high input impedance so it doesn't load the guitar, pedal or circuit that precedes it and have a low output impedance so it can drive the circuit, pedal or cable
that follows it.

There are three ways to bias a source-follower:
1. We can make the DC gate voltage zero volts and use Vp and Rs to set the bias.
2. We can make the gate voltage Vref and use Vref, Vp and Rs to set the bias.
3. We can DC couple the gate to the previous stage and use that stage's output voltage, Vp and Rs to set the bias.

Here's the Rat output buffer.

R8 and C9 ensure that the DC voltage on Q1's gate is 0V. Typical Vp for 2N5458 is -4V. That means Q1's source is close to 4V and the drain
current is...

(let's not always see the same hands, class)

Id = Vp / Rs = 4V / 10K = 400uA.

For the 2N5458, Vp can be between -1V and -7V, so Vs and Id can be all over the place. If Vs is at 1V or 7V, then we've lost a fair amount of headroom and we could end up with Q1 saturating. The only solution with this circuit is to cherry-pick Q1 so we get a Vp that is somewhere between 1/3 and 2/3 of the power supply voltage.

Here's the Covert output buffer.


It makes its own Vref with R18 & R19. Those two resistors bias Q5's gate to 1/2 Vcc (4.5V). Typical Vp is -1.75V. That puts the bias point at:

Vs = 4.5V + 1.75V = 6.25V.

Id = 6.25V / 4.7K = 1.33mA.

For the MPF4393, Vp ranges from -0.5V to -3.0V. That means Vs can be as low as 5V or as high as 7.5V. 5V is not bad, it's near the midway point between Vcc and ground. But 7.5V has only 1.5V of headroom and Q5 will saturate during the loud parts of the notes. Here, we have some freedom. We can adjust R18 or R19 to obtain the desired Vs or pick another JFET out of the pile.

Last example. This is the 3rd stage in the M800 OD.


Q3 makes the gain in the 3rd stage. Q4 is a buffer that keeps the tone stack from loading Q3. Q4's gate voltage is the same as Q3's drain voltage (because they're connected). Lucky us! We can use TRIM3 to dial-in Q4's bias point. Vp for the J201 is -0.3V to -1.5V. We can set TRIM3 to give us something around 5V at Q4's source, which puts Q3's drain around 4V. Then we tweak by ear from there.

I'll save mu-amps for part 2.

 

[lrgaraujo]

You'll know you have a decent match when Q5-D is between +5V and +5.5V.

Awesome! Is it gonna be approximately the same for the other mu-amp pairs?

 

[Chuck D. Bones]

No, because the source resistors (R16 & R24 in the circuit above) are all different ratios and you are not matching the transistors for Idss & Vp. I can only guess whether Catalinbread screened & sorted their JFETs.

 

[lrgaraujo]

Man, I love how jfets sound, but they definitely are too much for my head (you, sir, do make it more understandable, and I thank you)

 

[lrgaraujo]

Hello Chuck, it's me once again demonstrating my absolute lack of knowledge.

I have a bunch of 2sk304 that measure quite similarly to J201 in terms of Vp (between -0.6V and -0.8V) and Idss (close to 0.8mA for a lot of them), which I have been using in place of J201 in some breadboard projects with good success soundwise (they seem to bias ok as well).

Should I be worrying about other datasheet characteristics (such as transconductance) or do Vp and Idss describe everything we need well enough?

 

[Chuck D. Bones]

Vp and Idss tell us everything we need to know about operating a JFET in an audio circuit. If they bias correctly and sound good, then they are viable subs. Note that some pedal circuits are very finnicky (Fairfield Unpleasant Surprise, for example) and require a much lower Vp to work correctly.

Look at the 2nd equation above. Transconductance is determined solely by Vp, Idss and the circuit's bias point (Vgs or Id). The datasheet transconductance value is measured at an extreme condition (Vgs = 0) which does not normally occur in a pedal circuit.

 

[lrgaraujo]

Cool, thanks, Chuck! That's what I had gathered from the equations, but the datasheets confused me.

Too much information can be dangerous for the uninitiated

 

[Chuck D. Bones]

Too much information can be dangerous for the uninitiated

Indeed.
TMI can be confusing even to the experienced designer.

Something else to keep in mind about the datasheets: they mostly list performance limits. You will rarely find a part that has a parameter right at limit, and you will never find a part with all of the parameters at the limit.

 

[bowanderror]

Last example. This is the 3rd stage in the M800 OD.

View attachment 8904
Q3 makes the gain in the 3rd stage. Q4 is a buffer that keeps the tone stack from loading Q3. Q4's gate voltage is the same as Q3's drain voltage (because they're connected). Lucky us! We can use TRIM3 to dial-in Q4's bias point. Vp for the J201 is -0.3V to -1.5V. We can set TRIM3 to give us something around 5V at Q4's source, which puts Q3's drain around 4V. Then we tweak by ear from there.

After first spotting it in the preamp section of the Low Tide, I've been seeing this direct-coupled JFET-buffer setup a lot lately (Beetronics Fat Bee, JC-120 Preamp, JCM800 Emulator). Most of those circuits use it before a tone stack or into a power amp, and the Low Tide uses it to split signal to the LPG, BBD, & blend circuits. You mentioned the buffer prevents loading down Q3, and I'd guess you can get a pretty low output impedance from the buffer as well. Are there any other advantages to this arrangement? Will there be much of a difference between using a JFET vs. a BJT for the buffer?

The preamp section from the Low Tide is pretty simple, but I really love the way it sounds:


In LTSpice, it looks like the JFET drain is biased right around 4.5V:

I think main characteristics I like about this preamp is that it's super sensitive & pleasantly noisy, with only a little bit of what you might call overdrive. The gain is ~10dB, or ~16dB with the Boost switch on, and there doesn't seem to be too much filtering going on. Would I be correct in assuming the sound is primarily due to the use of a high gm (low Vp/high Idss) JFET?

I tried running through your math above for this circuit, does this look about correct?:

 

[Chuck D. Bones]

That preamp was designed to provide a high-impedance input, low-impedance output (to drive other parts of the Low Tide), clean, low-noise gain and a flat freq response. In other words, it should be transparent. If you're hearing overdrive then you're setting the gain too high for the pickup output. But hey, if you like it that way then go for it. This preamp should not be noisy. Are you sure you're not hearing BBD noise? I would not call 746μS "high gm." The preamp gain is determined by Q1's gm, R3, R4 & R52 (Low Tide sch ref).

Q2 could be a JFET or a BJT, it makes little difference in this circuit.

C4 does nothing in your sim because it's in parallel with an ideal voltage source (V2). Same goes for R1 & C1.

 

[steviejr92]

ive read this about 20 times aleady throughout this last week and i have to say i still dont fully understand it all, but this morning i felt i made more progress than any other day and im starting to understand much more than what i did even a day ago. i cant stress enough how valuable this is!

 

[micmac]

Hello Chuck, everybody,

In the first entry it says: "The only restrictions are Id has to be smaller than Idss ..."

Here's the link to the PedalPCB Simple JFET Buffer:

https://docs.pedalpcb.com/project/Buffer-TH.pdf

To me it looks pretty much the same as the Covert output buffer, except Rs is 3k3 instead of 4k7. The build doc calls for J201 or equivalent.

So if I apply the formulas from Covert example to the Simple JFET Buffer using a J201 with Vp of -0,83V I get:

Vs = 4.5V + 0,83V = 5.33V.

Id = 5.33V / 3.3K = 1.62mA.

If I compare Id to average J201 Idss of 0.64mA (as per ROG), then Id of 1.62mA is bigger than the Idss. So that would be contrary to the statement "The only restrictions are Id has to be smaller than Idss ...".

If I go with the Covert and I use a PN4393 that I have here that measures Vp = -1.24V and Idss = 10.95mA I get:
Vs = 4.5V + 1,24V = 5.74V.
Id = 5.74V / 4.7K = 1.22mA.

So in this case the Id _is_ smaller than Idss, so the statement "The only restrictions are Id has to be smaller than Idss ..." would be true.

Lots of people in this forum seem to have used the Simple JFET Buffer board and I suppose many used J201s. So I guess the statement "The only restrictions are Id has to be smaller than Idss ..." is not relevant for the buffer case, correct?

What is important for the Covert buffer and the Simple JFET buffer? With the gate at half the supply voltage we only have the JFET selection and we can put some Rs. What's the best JFET to pick, what's the best Rs? From Chucks writing I gather that it's preferable to pick a transistor with a small Vp. Is Rs important for the buffer case? Is Idss important?

 

[Chuck D. Bones]

The short answer to the Id question is yes, Id always has to be less than Idss because Id can never be greater than Idss.

The longer answer is that the peak Id must be less than Idss, where the peak drain current is the DC drain current plus 1/2 of the peak-to-peak AC drain current.

The desired Vp range depends on the specific circuit application. In the most general terms, we usually want to bias the JFET for maximum headroom.* That's certainly true for buffers since their job is to amplify current without coloring the tone. Some buffers bias the gate from ground. The Life pedal is an example. Actually, the Life pedal is an example of biasing done wrong. For maximum headroom, we want the source at 1/2 Vcc = 4.5V. If we bias a typical PF5102 from ground the highest Vs we can expect is around 1.3V since the max Vp for a PF5102 is -1.6V. This ok for Q1 since the guitar input signal will be less than 0.5Vp-p. We get into trouble with Q5 if we select the "no clipping diodes" option on the rotary switch. The signal going into Q5 can easily exceed 2.6Vp-p which means Q5 will clip on the negative half cycle. Maybe that's intentional, IDK.

Other buffers bias the gate from some voltage, usually 1/2 Vcc. The Covert is an example of this. Q5's gate is at 4.5V (when Vcc is 9V). Q5's source voltage is higher than the gate, probably around 1.3V higher. That puts Q5's source at around 5.8V. That means the drain current is around 1.2mA, well below Idss and the source voltage is 3.2V below the 9V rail. Give that we lose at least 5dB (typically 10dB) in the tone stack, we'll have plenty of headroom. For maximum headroom, R18 or R19 could be adjusted to get Q5-S at 4.5V.

Now let's look at the PPCB Buffer. The J201's gate is biased to 4.5V. The max Idss for a J201 is 1.0mA. I have measured Idss from 0.2mA to 0.85mA in my J201 stash. If we try to bias the source to 4.5V, the drain current will be 4.5V / 3.3K = 1.36mA, which ain't gonna happen because Idss is limited to 1mA or less. Three options:
1. Bias the gate to a lower voltage so that Id is < Idss for the particular J201 being used.
2. Increase the source resistor so that Id is < Idss for the particular J201 being used. Depending on the J201 you have, that resistor could be 22K or larger.
3. Use a different JFET with a higher Idss.
I favor door #3.

* not always the case and some circuits deliberately bias the JFETs for maximum dirt.

 

[micmac]

Thank you Chuck! Like everybody else I appreciate you sharing your insights!

 

[LukeFRC]

Right - stupid question time...

I found a schematic online, and the guy warns, "you need to know how to bias a JFET and to socket the source resistor to bias it... "

The first stage of the pedal is pretty much the same as the start of a Barbershop/Chopshop - which in Pedal PCB land has a trim pot at the drain to bias... so I'm reading this thread, scratching my head and trying to work out why PCB's do brain vs source for bias.

 

[Chuck D. Bones]

"brain vs source" indeed. If only this %$&^ phone had a proper keyboard!

But seriously folks, we can dial-in the bias by adjusting either the source or drain resistor. But, we can't go too far up or down with either resistor before the circuit won't work the way it's supposed to work. The one downside to using a trimpot on the source side of the JFET is sometimes, depending on the circuit, the drain voltage is very slow to respond to changes in the trimmer. I have a pedal like that with four JFETs and four trimpots. The trimming procedure included some colorful language. My preferred method is to not use a trimpot at all. I breadboard the part of the circuit around the JFET in question, put in what would be the correct* resistor value that the trimpot is trying to approximate and then audition JFETs. Once I get one that's close, then I fine tune the bias by stepping the resistor up or down a little.

* How do we know the "correct" resistor value? We find someone who has a production pedal and ask them.

 

[LukeFRC]

"brain vs source" indeed. If only this %$&^ phone had a proper keyboard!

But seriously folks, we can dial-in the bias by adjusting either the source or drain resistor. But, we can't go too far up or down with either resistor before the circuit won't work the way it's supposed to work. The one downside to using a trimpot on the source side of the JFET is sometimes, depending on the circuit, the drain voltage is very slow to respond to changes in the trimmer. I have a pedal like that with four JFETs and four trimpots. The trimming procedure included some colorful language. My preferred method is to not use a trimpot at all. I breadboard the part of the circuit around the JFET in question, put in what would be the correct* resistor value that the trimpot is trying to approximate and then audition JFETs. Once I get one that's close, then I fine tune the bias by stepping the resistor up or down a little.

* How do we know the "correct" resistor value? We find someone who has a production pedal and ask them.

Thanks! that makes sense

It was someone looking at a small sound big sound mini - and seeing how similar it is to the pedal pcb chop shop (barbershop) I had made I was confused how differently they were biased.

When I built the barbershop my test jig for trying to measure the ldss of 20 smd j201 was utterly painful - I didn’t even bother with vgs - it would have broken me!

 

[LukeFRC]

"brain vs source" indeed. If only this %$&^ phone had a proper keyboard!

Or not stupid autocorrect!

 

[Chuck D. Bones]

When I built the barbershop my test jig for trying to measure the ldss of 20 smd j201 was utterly painful - I didn’t even bother with vgs - it would have broken me!

It gets easier the more you do it.

 

[mcf]

Thanks for the excellent article. Another resource I found quite helpful is chapters 10 and 11 from https://eng.libretexts.org/Bookshel...fect_Transistors_(JFETs)/10.2:_JFET_Internals

Id = Rs / Vp = 4V / 10K = 400uA.

This should be Id = Vp / Rs = 4V / 10K = 400uA, of course. But to match the sign with the earlier definition (Vp = -4V), maybe it's better to write -Vp / Rs?

The transfer function (drain current vs. gate voltage) of a JFET is:

If we do a little calculus, we can solve for the transconductance (gain):

I'm a bit confused about the negative sign here, though perhaps it doesn't matter. Here's my math:

Since a small increase in Vgs results in less negative bias and larger current, it makes sense to me we'd get positive gM, and this matches what I've seen in other articles. I know it's just a small detail, but I just want to make sure I understand what's going on.

 

[Chuck D. Bones]

Rs / Vp is a typo. Pretty sloppy on my part.

For a JFET operating in the linear mode, Vgs & Vp will always have the same sign. We frequently use a positive number to represent Vp in an N-channel JFET, but this is shorthand with the understanding that Vp is negative in an N-channel JFET. The transfer function formula above is valid only when Vgs / Vp is between 0 and 1. Below zero, Id = Idss and above one, Id approaches zero. It's never exactly zero because of leakage in real-world devices.

I also screwed-up the formula for Gm. When I swapped the order of 1 - Vgs/Vp I should have dropped the - sign up front. Your formula is correct.

I appreciate that you read and understood what I wrote and took the time to point out my errors. They have been corrected.