Mini Heterodyne Receiver is never quiet

den_vom_moersch

New member
Hi,
so I finished my Mini Heterodyne Receiver built. And here is my Problem.
There is always a strong noise that overlays everything.

I traced the signal path and found that the signal gets more and more distorted in the first three stages of IC2 (CD4069UBM). After the third stage of IC2 the noise is so loud, even without an input signal attached. I think that is not the way the pedal should respond after the videos I watched.

I have already checked the values of the components and the solder joints.

Can it be due to the carbon layer resistors or have I fried the IC2?
Why does it produce this noise on its own without an input signal?
What is the purpose of the three stages in series?

Ive measured the voltages on the first three ICs.

Vref = 9V
IC1
1: 4.16
2: 4.16
3: 4.16
4: 0
5: 3.6
6: 4.16
7: 4.16
8: 8.3

IC2
1: 3.85
2: 3.85
3: 3.85
4: 3.85
5: 3.79
6: 3,80
7: 0
8: -
9: -
10: -
11: -
12: -
13: -
14: 8.3

IC3
1: 3.8
2: 5.8 - 6.5
3: 4.0 - 5.0
4: 3.4 - 3.8
5: 0
6: -
7: 0
8: 8.3
9: 0 - 3.5
10: 0 - 8.3
11: -
12: -
13: -
14: 8.3

Thanks in advance, maybe someone can support me getting rid of the noise or whatelse I could check.
 

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Last edited:
Is the noise a constant pitch, or does it fluctuate?

Is it 50/60hz or one of its harmonics (100/120; 150/180; 200/240; etc…)? If so, it’s likely power supply noise that’s just being amplified at each of the gain stages. For reference, 50/100/200hz is Roughly Ab, 60/120/240hz is roughly B. 150hz is right between D and Eb, 180hz is between F and Gb. If any of those line up with the noise you’re getting, try a different power supply first. I haven’t built the MHR, but it’s a PLL style pedal, and every PLL pedal I’ve used has been extremely sensitive to bad power
 
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I've been poking around at my own MHR. It doesn't sound much like my EQD data corrupter. I'm currently posting without finishing my thought. On purpose.

Ahem. Where was I...

I'm curious about C9-11 & C13. It looks like these are supposed to be power supply decoupling caps for ICs 2, 3, 4, & 6.

In my build, I used PPS 100nf caps for these. It worked just fine when I got everything online, except that the glide function would go CRAZY and the circuit would respond wildly without any of the predictable repeatability characteristics of the data corrupter.

So I'm curious...in my independent study of decoupling caps, it appears that best practices indicate using as short of a path as possible, with as diminutive of a capacitor as is feasible.

That is to say, take the shortest path possible between the rails, as close to the IC as possible, and use a cap with as high of a dialectric constant as possible. The practical upshot: to make the path between rails as minimally inductive as possible, to enable the capacitor to react to transients (noise)in the power supply as quickly as possible.

But...I don't know how important this is for our purposes. This is just my current understanding based off my google surfing.


That being said, though, I'm curious if X7R MLCCs would be the better option in these positions, as the absolute capacitence . I'm considering swapping out these caps on my build...

Although hell, could be that I fried one of the SMD chips.
 
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Ok, I recorded the noise for better understanding.
Clip 1 - Warning - 🤯LOUD NOISE - was recorded with an audio probe after each stage of IC2. You can hear the increase in the noise level. No_input_3_Stages
Clip 2 was recorded at the output of the pedal with a guitar at the input. The same noise can be heard between each note played. pedal_with_guitar_signal

Edit: I tested two different power supplies - the result stays the same
 
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