Hello everyone,
In the idle state without an audio signal, could the voltage between the gate and source of transistor Q1 depend on the position of the attack and release potentiometers? I measured the Vgs off for my JFET, but I'm having trouble setting it with potentiometer TR1. While I can adjust the voltage drop from 0 to 5 V directly on the TR1 itself, the Vgs of Q1 fluctuates randomly, depending on the TR1 rotation, but I can't reach the target Vgs off+0.01 V. What voltage should be at the gate of Q1 relative to ground in the idle state? Should it be fixed around Vref?
The rest of the circuit seems to be working properly. The input and output buffers, the blend control, the compression gain, the tone control, and the current source on Q2 seems to be OK. The section from the output of IC3.1 through the attack and release potentiometers to the input of Q1 is suspect. I don't get this part of the circuit and don't know what to expect there.
I have built the circuit on a perforated board. So I may have some wiring errors. Premanufactured PCB was too big for my enclosure and the shipping cost for my country was too high.